Source-synchronous I/O links using Adaptive Interface Trainings for High Bandwidth Applications

• Applicant: Professor Dr.-Ing. Klaus Hofmann
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2015 to 2019
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 269885131

Due to rising demand on computation, high bandwidth communication is nowadays required at all levels of data communication systems. In general, two clocking schemes for transmitting and receiving high speed data are used: clock-data-recovery (CDR) and source-synchronous. Whereas CDR systems currently achieve higher per lane data throughput due to the higher symbol rate, its limitations are the high effort and also high power need for recovering the clock at the receiver side. Source synchronous clocking is used for parallel interfaces, transmits one or more clocks, does not need a receiver PLL and is therefore inherently more robust than CDR techniques. The problems that need to be overcome are channel nonidealities (crosstalk, ISI, Signal Integrity and especially the phase-relationship between clock and data). Whereas CDR provides superior per lane performance regarding throughput, source-synchronous data transmission can be superior regarding throughput, power and circuit simplicity if parallel links (up to 32 or more channels) are used. This research proposal aims to investigate the combination of various methods for increasing the data rate of source synchronous systems, such as energy efficient clock synchronization scheme using a digital unit-delay incrementer, employing adaptive algorithms for equalizer training beyond state-of-the-art (LMS equalization), Advanced hybrid I/O calibration algorithms for differential and single-ended I/O-systems, Data encoding especially for single-ended I/Os, and especially the combination of the individual measures. Due to the previous work done at system modeling and abstract circuit level we expect a power efficiency of about 1mW/Gbps or better, but need the proof by demonstrating the combination of the approaches in a silicon demonstrator. With this research proposal we aim to investigate the principle boundaries of the source-synchronous communication approach. The results of this research proposal can be used in various scenarios, from on-chip data communications, Chip-PCB-Chip and flexible, cable-based connections.

• DFG Programme: Research Grants