Reconfigurable Architectures and Real-Time Systems Co-Design for Non-Volatile Main Memory (ARTS-NVM)

• Applicants: Professor Dr. Jian-Jia Chen; Professor Dr.-Ing. Jörg Henkel, since 10/2024
• Subject Area: Data Management, Data-Intensive Systems, Computer Science Methods in Business Informatics
• Term: since 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 502308721

Recent embedded systems demand high computation, low power consumption, and large memory footprint, which drives methodologies of embedded systems towards disruptive memory architectures like byte-addressable non-volatile memories (NVMs). However, their new characteristics also impose vastly different design challenges. For example, the limited write endurance demands a new treatment in the memory management, which motivates various techniques across different system layers to mitigate the stress of using NVM as main memory. Yet, the prior knowledge in worst-case timing analyses for real-time systems has hardly been explored with respect to NVM. This research project aims at developing reconfigurable architectures and sound timing analyses that can safely utilize NVMs as main memory in real-time embedded systems by improving the timing predictability and the quality of wear-leveling system routines. Although there have been significant efforts in investigating disruptive design issues and worst-case timing analyses, their intersections yet cannot model and analyze the system behaviors when utilizing NVMs as main memory in real-time systems. With the evolution of embedded systems, large memory space and low power consumption are foreseen to be in high demand in the near future, thereby aggravating the need for NVM-friendly real-time operating systems. In this proposal, we plan to target the following goals: i) Provide suitable task models and approximation approaches to derive safe upper bounds on the worst-case execution time and the worst-case response time under the characteristics of NVMs. ii) Propose hardware/software co-design approaches to develop WCET-aware memory controllers and near-memory accelerators for improving the wear-leveling algorithms while satisfying given real-time constraints. iii) Enhance system software to effectively adjust scheduling policies during runtime through developed NVM-friendly facilities and emulate the presence of not-yet-available NVM technologies in RTOSes. These goals are motivated by the fact that emerging byte-addressable NVMs exhibit various new characteristics, which impose new challenges in memory management, data retention, reliability, and wear leveling. The proposed solutions in the literature indeed have addressed the technical issues. Considering their required time overhead, however, little attention has been paid for the timing predictability. How to mitigate the stress of the NVM under given timing requirements is still an open question. In this project, we take the usage of NVM as main memory into account from the early design stage, and we devise novel insights for methodologies, analyses and optimization. We anticipate that the research results of our project will provide a new perspective on real-time embedded systems for disruptive memory technologies with timing-aware reconfigurable architectures, and enrich the outreach of the scientific results of SPP 2377.

• DFG Programme: Priority Programmes
• Subproject of: SPP 2377: Disruptive Main-Memory Technologies
• Ehemaliger Antragsteller: Dr.-Ing. Lars Bauer, until 10/2024