Project Details
Projekt
Self-adaptive Coarse-Grained Reconfigurable Architectures as Reliability Enhancers in Embedded Systems
Applicant
Professor Dr. Wolfgang Rosenstiel (†)
Subject Area
Computer Architecture, Embedded and Massively Parallel Systems
Term
from 2010 to 2015
Project identifier
Deutsche Forschungsgemeinschaft (DFG) - Project number 181827175
The overall objective of the ARES project is the development of low-cost reliable embedded systems by means of adaptive error handling methods. On the way to our overall goal, we have developed methods for error detection and repair in the previous phases of the project, that are based on coarse grained reconfigurable architectures. Thus, we have created a very reliable and efficient component of the overall system, which can be used as an intermediary between the underlying technological layer and the overlying application layer. Thereby it is particularly suitable for adaptive cross-layer error handling. The following three objectives for the next phase of the project derived from these characteristics: The first goal is to access the technology layer. It is intended to investigate how errors on the technology layer can be detected early, and how these errors can be reported to higher levels for error correction. Furthermore, we plan to investigate how faults can be detected before they emerge. Then direct countermeasures can be initiated to avoid erroneous behavior at a higher abstraction layers. We will use the new FDSOI technology, that provides the ability to change the threshold voltage at run-time and thus complements our adaptive approach perfectly. The second objective is to access the application layer to enable the application-dependent use of the technology layer for error handling. The third objective is the development and production of a chip that covers test structures to demonstrate the benefits of our methodology in silico under stress conditions quantitatively. By achieving these goals, we will be able to provide a reliability methodology for industrial use and also for further research, that increases the reliability at low cost and low energy consumption, and thus offers the possibility to extend the CMOS era.
DFG Programme
Priority Programmes
