Leveraging new hardware concepts and prototype technology available through the cooperation of the Jülich Supercomputing Centre with the hardware industry, this project addresses the challenges of immense parallelism, hybrid architectures and increasingly complex memory organisation by testing and developing new hardware-oriented algorithmic approaches. This includes increasing parallelism through additive or asynchronous multigrid as well as parallel-in-time integration within the Hybrid Monte Carlo process, fault resilience and Cluster-Booster concepts for valence computations. Managing of data on emerging architectures will also be considered.
DFG Programme
CRC/Transregios
