Aging-Inclusive Simulation Framework for IMC Application: Investigating Reliability Trade-offs in Next-Generation Memory Architectures (AFMC)

• Applicant: Dr.-Ing. Supriya Chakraborty, Ph.D.
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2024
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 550357292

Recent advancements in the field research and developments have proved that ReRAM devices are a promising contender for future applications. ReRAM devices integrated with CMOS technology to form 1T1R cells and crossbar array structures have a wide application spectrum including neural network, in-memory computing, neuromorphic computing, hardware security, etc. However, these emerging devices are susceptible to reliability issues including limited endurance and temporal variations. These challenges significantly affect the performance of the devices during their lifetime and pose a bottleneck for using them in the mainframe applications. Moreover, CMOS devices are also prone to aging effects leading to performance degradation during their lifespan. The goal of this project is to comprehensively investigate the aging-induced errors in analog ReRAM devices and analyse its impact on performance and reliability during IMC application. In particular, the objective of the proposed project is to develop an aging induced simulation framework for IMC application encompassing the manufacturing and process variations of the device, temporal variations, degradation of CMOS and ReRAM devices due to aging, in-field faults, and lifespan of the architecture. The initial phase of the project focuses on developing an accurate aging model for redox-based ReRAM devices to accurately represent their endurance degradation. This model will then be integrated into the compact model of ReRAM devices for circuit simulations, considering various environmental conditions. Subsequently, a comprehensive analysis of in-field faults generated due to endurance degradation of both CMOS and ReRAM devices will be conducted. This analysis aims to identify and characterize various types of faults that may occur during the operational lifespan of these devices, providing insights into their impact on system reliability and performance. An accurate in-field fault model developed from the analysis will be incorporated in an open-source simulation framework of IMC architecture and investigate the effect of in-field faults for IMC applications. Finally, refinement of the simulation framework will be performed to develop a comprehensive framework for IMC applications. The initial results obtained from the proposed project are envisioned to provide a benchmark of realistic fault models that can help in detecting faults in ReRAM/CMOS technology in the early stages. This proposal serves as a foundation in developing cutting-edge testing methodologies and implementing advanced fault-mitigating strategies to ensure high-quality product outcomes.

• DFG Programme: WBP Position