High-Efficiency Radiation-Hard Power Converter System for Space Electronics and Inner Layer of Particle Physics Experiments

• Applicant: Professor Dr.-Ing. Michael Karagounis
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering ; Nuclear and Elementary Particle Physics, Quantum Mechanics, Relativity, Fields
• Term: since 2024
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 546567423

The overall goal of the joint project between National Taiwan University (NTU) and the Fachhochschule Dortmund (FHDO) is to improve the power efficiency of electronic systems in radiation-exposed environments such as space and the inner layers of particle physics experiments. Pixel detectors are semiconductor devices used in the inner layers of the ATLAS and CMS high-energy physics experiments at CERN's Large Hadron Collider (LHC) in Geneva, Switzerland, to record the path of short-lived particles created by particle collisions near the point of interaction. Due to space and material constraints, as well as the challenging environmental conditions in the experiments, only 20% power efficiency is currently achieved. Power efficiency is also a critical factor in space electronics as it directly affects the mass required to generate, transport and store energy. High power efficiency allows a larger mass budget for payload instruments and/or a reduction in the overall mass budget of satellites. It improves maneuverability and mission flexibility, reduces launch costs, and improves battery health, thereby extending satellite life and mission. The power efficiency will be improved by implementing a power supply scheme based on cascaded two-stage DCDC step-down conversion from 28V to 3.6V and 3.6V to 0.9V with an overall efficiency of 80% including the power dissipation of the converters and IR losses in the power distribution network for a total load current of 16A. FHDO will design radiation-hard high-frequency step-down DCDC converters with stacked transistor switching stage and conversion factor 4 in the 28nm node. NTU will design a high voltage DCDC converter in 180nm BCD technology to achieve a high conversion ratio. An AI/ML-based optimization methodology will be used to design multi-phase and resonant multi-level step-down converter prototypes. The framework will support converter architecture, modulation and control scheme studies. The converter circuit description will be generated in textual Verilog-A form from a generator that allows the circuit structure to be defined at an abstract level. Abstract parameterized Verilog-A models will be developed for the modulation and control circuitry and combined with parameterized transistor-level schematics of the switching stage and lumped models of the LC tanks. Figure of merits can be derived from the simulation by formulating measure expressions provided by circuit simulators. This approach allows the use of architecture search algorithms known from artificial neural network design. For computationally expensive optimization problems, algorithms that model the objective function using a probabilistic surrogate function are preferred to reduce the number of objective function evaluations. Multi-Objective Tree Parzen Estimator-based Bayesian Optimization will be used as a starting point in this project.

• DFG Programme: Research Grants
• International Connection: Taiwan
• Partner Organisation: National Science and Technology Council (NSTC)
• Cooperation Partner: Professor Dr. Yi-Jan Emery Chen