Matrix Analogue-to-Digital Converters with Frequency and Time Interleaving

• Applicant: Professor Dr.-Ing. Frank Ellinger
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering ; Communication Technology and Networks, High-Frequency Technology and Photonic Systems, Signal Processing and Machine Learning for Information Technology
• Term: since 2024
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 545790440

Analogue-to-digital converters (ADCs) limit the data rates for future communications. Time interleaving (TI) increases the sampling rates by parallelisation of multiple (n) paths but is limited by jitter and path mismatch problems. M A D C explores novel techniques breaking these barriers. TI is combined with frequency-interleaving (FI) with m paths enabling matrix interleaving. This decreases the sensitivity of TI regarding jitter and mismatch, because the input is channelized into smaller sub-bands. Hence, higher overall sampling rates are possible. However, novel challenges arise regarding nonlinearities (e.g. due to harmonic mixing and convolution) and noise associated with the broadband FI band splitting, mixing and combining. UC Berkeley demonstrated an FI ADC system with 9 channels, input signal of 25 GHz and 6 bit, an analogue CMOS frontend and commercially available ADC cores. M A D C investigates novel ADC concepts to show the feasibility of record input frequencies up to 75 GHz and sampling rates up to 150 GS/s at 7 bit. Multidimensional parameter rooms including n, m, bandwidths per path, mixer, local oscillator (LO) frequencies, and clock frequencies are investigated by a tailored simulation platform. Optima are searched considering all relevant imperfections of devices and assemblies such as harmonic mixing interferences, jitter, time, phase and amplitude misalignments of different paths e.g. on signal-to-noise-ratio. Answers will be searched for questions such as: how to split frequency bands in best way, what effects do frequency band overlaps have, which harmonic rejection means and filters types are best suited, what are the limits of digital signal processing, etc. Based on the gained knowledge, also concepts are studied to synchronise the clock and multiple LO frequencies, to superposition path data and to correct nonidealities in analogue as well as digital domain. A system with up to 8 FI paths is optimised using SystemVue and Cadence circuit simulations. The key circuits such as the dividers, amplifiers, mixers (linear and harmonic rejection based), optimised ADC-cores, filters, digital serial interfaces are designed. IHP SG13G3Cu is applied for the analogue and GF 22FDX for the mixed signal and digital parts. For the ADC paths, we build upon our recent design in 22FDX showing by simulations for a 16 × TI SAR (successive approximation register) ADC a sampling rate of 10 GS/s and an input frequency of 5 GHz at 7 bit and only 18 mW. Novel circuit concepts are proposed, e.g., for an FI-splitter based on distributed amplifiers with gm-peaked triple-cascodes to solve the input frequency bottleneck at low dc power. To prove the concepts also by hardware, test systems are designed on basis of tailored boards including the designed chips, FPGAs and measured with the fastest available measurement equipment. M A D C combines competences of Ellinger in RF/analogue and Matthus in digital/ADC IC design.

• DFG Programme: Research Grants