Design Obfuscation with Sequential Timing to Counter Reverse Engineering

• Applicants: Professor Dr.-Ing. Bing Li; Professor Dr.-Ing. Ulf Schlichtmann; Professor Dr.-Ing. Georg Sigl
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: since 2024
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 530539871

Integrated circuits have been widely applied in various safety­-critical systems such as autonomous driving. Therefore, the protection of the design of integrated circuits has become a high priority for security and economic reasons. A major threat to the design of integrated circuits comes from reverse engineering, in which authentic chips are purchased from the market and delayered. The layers are then imaged to recognize logic gates and flip­-flops as well as their connections in order to reconstruct the netlist. With such a netlist, the original design can be counterfeited and Trojans can be inserted into the counterfeited chips to compromise user systems. To protect circuit netlists against reverse engineering, various techniques have been proposed by the research community, e.g., logic locking, gate camouflage, etc. These methods, however, face serious challenges such as SAT attacks. In this project, we will explore netlist camouflage on the sequential level to protect circuits. The proposed concept invalidates the fundamental assumption that a netlist sufficiently represents the functional information of a design. On the one hand, flip­-flops in the original circuit will be selectively removed to construct wave-pipelining paths. On the other hand, buffers and latches created by changing doping of original flip-flops will be inserted to obfuscate single­-cycle paths. Consequently, the flip-flops recognized in reverse engineering do not correspond to the actual signal synchronization in a circuit. In addition, delay camouflage of combinational paths will be introduced to prevent the actual signal synchronization from being recognized. Furthermore, the protection of finite state machines with embedded timing information will also be explored to counter reverse engineering and probing attacks. The proposed techniques will combine naturally with existing methods camouflaging combinational gates and their effectiveness will be evaluated using attacks based on SAT and machine learning.

• DFG Programme: Research Grants
• International Connection: China (Hong Kong)
• Cooperation Partner: Professor Dr. Bei Yu