Khunjerab: Bridging Applications and Future Emerging Memory for Different Performance-Power-Reliability Trade-Offs

• Applicants: Professor Dr. Holger Fröning; Professor Dr. Vincent Heuveline
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems ; Mathematics ; Software Engineering and Programming Languages
• Term: since 2021
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 449797478

Along with fundamental scaling limitations of CMOS transistors are approaching, the need of data-intensive computing is exceedingly difficult to be met, especially costly off-chip accesses to dynamic random-access memory (RAM) became a major issue in reducing performance and power efficiency. The on-chip memory structure with both delighted features, storage and compute, may be the breakthrough in the very near future. While there are various technology alternatives under consideration in research and development, most of them are still nascent and the implications on complete compute stack still need be understood. Resistive RAM (RRAM), known as memristor, is a particular example of such a memory technology. RRAM can integrate storage and computation in the same physical location, which makes it a promising candidate for a continued device size scaling with standard CMOS process. Still, there are a couple of notable shortcomings, including reliability as RRAMs are inherently unstable, variability in manufacturing that substantially impacts performance, and durability as lifetime is limited due to wear-off during write operations. Ultimately, there exists a huge space of possibilities, based on different design parameters, potentially resulting in unsafe designs of high performance but low reliability. Due to the present drawbacks of RRAM, the future memory architecture is most likely heterogeneous, thereby exploiting the best mix properties of a given technology will be required.In order to understand the implications of memristor on compute stack, and to establish a workflow that supports such technology, we propose a joint research that gathers expertise covering applications, hardware architecture, memory device design, and associated methods and tools such as optimization, compilation, mapping, and simulation. In summary, the stack from representative applications to future emerging processors based on novel memory technologies is covered, thereby enabling a deep understanding of memory technology with regard to required heterogeneity, in-memory computations, performance-power-reliability (PPR) trade-offs, and a similar understanding of suitable workflows to integrate such technology in compute systems and how applications can benefit from such technology.The proposed research considers a set of demanding applications covering in different engineering areas, including image segmentation, fluid dynamics, quantitative finance, differential operator approximation and other neural network applications, multiple models of RRAM design alternatives, and a processor simulation environment for a performance assessment in terms of execution time and power consumption. This tool stack is the foundation of investigations of heterogeneous memory,in-memory computations, and PPR trade-offs.

• DFG Programme: Research Grants
• International Connection: China
• Partner Organisation: National Natural Science Foundation of China
• Co-Investigator: Chen Song, Ph.D.
• Cooperation Partners: Dr. Kai Xi; Professor Jiawei Zhang