Project Details
Projekt
Cryogenic Complementary Metal-Oxide-Semiconductor Technology for the Realization of Classical QuBit-Control Circuits
Subject Area
Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
Term
since 2019
Project identifier
Deutsche Forschungsgemeinschaft (DFG) - Project number 422581876
Quantum information technology holds promise to unleash enormous computational power to solve problems that are intractable on today's classical computers. However, the realization of a useful quantum information processor (QIP) will involve a large number of coupled qubits. The reason for this is that each logic qubit consists of a large number of physical qubit implementations in order to establish an appropriate error correction utilizing e.g. surface codes. Each of the physical qubits requires a control unit that provides readout, gate pulses and bias parameters. One major challenge is that the most promising approaches for the realization of solid-state qubits are operated at cryogenic temperatures, which limits the available cooling power per qubit to very low values in the micro- to nanowatt regime. Typical experiments are controlled by external circuits located at room temperature, or at least at a temperature higher than that of the qubit. Extending this approach to the required number of qubits appears completely unpractical because of interconnectivity and size considerations. An integrated approach with microfabricated classical and quantum hardware in close proximity is thus very attractive. However, integrating classical control electronics close to the actual qubit chip requires the control electronics to be operated at a temperature of ~1K (while performing similar to state-of-the-art CMOS circuits) at an ultra-low power level. As a result of the limited cooling power, cryogenic CMOS circuits have to be operated at very low supply voltage in the tens of mV regime. This implies that extremely steep inverse subthreshold slopes, a very tight control of the threshold voltage as well as very low variability are required which is impossible to be achieved by simply cooling down the existing technology, optimized for room-temperature operation. The present proposal is a continuation of a project that has been targeting the exploration and development of a dedicated, cryogenic CMOS (cCMOS) technology and the fabrication and characterization of field-effect transistors based on this cCMOS technology. Within the preceding project we were able to show two promising ways to obtain steep slope cryogenic FETs and studied ways how to avoid dopants in such devices. Here, we aim at further developing the approaches and combining them in order to realize cCMOS steep slope devices.
DFG Programme
Research Grants
Co-Investigators
Professor Dr. Hendrik Bluhm; Dr. Lars Reiner Schreiber
