High yield, low variability – Employing silicon CMOS technology for the realization of spin qubits title of project extension: Tunable dielectrics enabling the co-integration of cryo-electronics and spin-qubits on the Si/SiGe platform

• Applicants: Professor Dr. Joachim Knoch; Dr. Lars Reiner Schreiber
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering ; Experimental Condensed Matter Physics
• Term: since 2019
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 421769186

The up-scaling of qubit chips with a handful of qubits toward a general-purpose quantum information processor requires millions of physical qubits. The implementation, tuning and coupling of all these qubits requires a classical control electronics that is located in the immediate vicinity of the qubits. Due to the very low cooling power available in fridges at cryogenic temperatures, the classical control electronics needs to operate at an ultralow power level. However, electrostatic disorder in the vicinity of gate-defined semiconductor spin qubits as well as at the semiconductor dielectric interface of cryogenic MOSFETs plays a crucial role for the functionality of both types of devices. For instance, the disordered potential leads to what is called band tailing that deteriorates the switching of cryogenic MOSFETs prohibiting the necessary reduction of the operational voltage (and hence of the power consumption) of the cryogenic electronics. Another important road block of cryogenic electronics is device-to-device variability of the threshold voltage. Furthermore, in the first part of the current proposal we were able to show that spin qubits located further away from each other can be coupled with a so-called shuttle device consisting of coupled quantum dots. Reducing disorder would strongly improve the capability of the shuttler to couple qubits coherently. Since mitigating disorder and tuning the threshold voltage are both essential for the functionality of the quantum dot and qubit as well as MOSFET devices, the issue needs to be addressed on the same footing in order to allow a co-integration of cryogenic electronics and qubits onto the same chip. In the present continuation of the project we will address the issues mentioned with the realization of a low-disorder and tunable gate dielectric that contains chargeable states (realized either with a dielectric stack consisting of several dielectric with different band gaps or with a metallic floating gate electrode). Applying appropriate gate voltages allows charging and discharging these states in order to shift the threshold voltage for each individual device (qubit or MOSFET). Optimization of an appropriate gate dielectric stack will be carried out with the fabrication and characterization of MOS-capacitors, MOSFETs and shuttle devices. Eventually, we aim at demonstrating a co-integration of a shuttler with an asymmetric sensing dot as read-out element whose output is amplified by cryogenic MOSFET in immediate vicinity on the same chip.

• DFG Programme: Research Grants