Multi-Valued Physical Unclonable Functions
Final Report Abstract
The goal of the present project was to exploit the multi-valued nature of Physically Unclonable Functions (PUF) to increase the extracted entropy per PUF unit compared to the state of the art. During this project we could improve the robustness of FPGA based ROPUFs for 16.4% and publish a large set of extracted responses. Based on these readouts a normalization and multi-valued symbol extraction was established, by dividing the probability-density function into intervals each representing a symbol. This increased the extracted entropy per PUF-cell by a factor of three. To minimize the influence of temperature variations we investigated a correction approach using polynomial interpolation. In addition error correction helper data schemes could be transferred from binary case to the multi-valued case. Via a variation of the code rate, a trade-off between information that can be extracted as key and error rate (reliability) is enabled. Based on this the security level for the different coding techniques was investigated and the leakage reduced to zero. Applying soft-decision algorithms increased the extract-able information compared to the error rate further. Another improvement using signal shaping is currently in the process of publication. A modular PUF coding chain was implemented for easy evaluation of all processing steps on one system.
Publications
- “Channel Models for Physical Unclonable Functions based on DRAM Retention Measurements”. XVI International Symposium Problems of Redundancy in Information and Control Systems (2019)
Sven Müelich et al.
(See online at https://doi.org/10.1109/REDUNDANCY48165.2019.9003355) - “In-depth Analysis and Enhancements of RO-PUFs with a Partial Reconfiguration Framework on Xilinx Zynq-7000 SoC FPGAs”. 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST). May 2019, pp. 238–247
Andreas Herkle et al.
(See online at https://doi.org/10.1109/HST.2019.8740832) - “Modular PUF Coding Chain with High-Speed Reed-Muller Decoder”. In: 2019 IEEE International Symposium on Circuits and Systems (ISCAS). 2019 IEEE International Symposium on Circuits and Systems (ISCAS). May 2019, pp. 1–5
Holger Mandry et al.
(See online at https://doi.org/10.1109/ISCAS.2019.8702484) - “Comparison of Measurement and Readout Strategies for RO-PUFs on Xilinx Zynq-7000 SoC FPGAs”. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE. 2020, pp. 1–5
Andreas Herkle et al.
(See online at https://doi.org/10.1109/ISCAS45731.2020.9181272) - “Multi-Valued Physical Unclonable Functions based on Dynamic Random Access Memory”. In: The International Symposium on Memory Systems. 2020, pp. 126–136
Sven Müelich et al.
(See online at https://doi.org/10.1145/3422575.3422787) - “Normalization and Multi-Valued Symbol Extraction From RO-PUFs for Enhanced Uniform Probability Distributions”. In: IEEE Transactions on Circuits and Systems II: Express Briefs 67.12 (Dec. 2020), pp. 3372–3376
Holger Mandry et al.
(See online at https://doi.org/10.1109/TCSII.2020.2980748) - “A Multilevel Coding Scheme for Multi-Valued Physical Unclonable Functions”. In: IEEE Transactions on Information Forensics and Security 16 (2021), pp. 3814–3827
Sven Müelich et al.
(See online at https://doi.org/10.1109/TIFS.2021.3089883) - “Using Polynomial Interpolation for Reproducing Multi-Valued Responses of Physical Unclonable Functions on FPGAs”. In: 2021 IEEE International Symposium on Circuits and Systems (ISCAS). May 2021, pp. 1–5
Holger Mandry et al.
(See online at https://doi.org/10.1109/ISCAS51556.2021.9401501) - “A New Helper Data Scheme for Soft-Decision Decoding of Binary Physical Unclonable Functions”. In: IEEE Access 10 (2022), pp. 12644–12653
Robert F.H. Fischer and Sven Müelich
(See online at https://doi.org/10.1109/ACCESS.2022.3146989)
