A novel high-speed and low power ADC based on a tracking ADC suitable for the implementation in general ultradeepsubmicron technologies
Final Report Abstract
With this project „Algorithmic Tracking ADC” we investigated the impact of increasing the digital clock while keeping the delay of the analog comparator constant, so that there are multiple digital steps within the delay of the analog components. As a result with the right choice of parameters and design of the components (e.g. digital counter, digital postprocessing, selection of voltage jump height in the feedback path, compensation of nonlinearities) a performant and KPI-wise capable ADC has been designed, which can be either configured as a Tracking ADC, but also a Digital Ramp ADC or even a SAR-ADC. As predicted and to no surprise, we could show that with a fast digital counting frequency significantly beyond the delay of the analog feedback path (comparator and DAC) the data rate at the output of the ADC could be significantly improved. At the same time we could show that other, less expected key properties of the ADC (such as the PVT-dependencies of especially the analog components) could be significantly improved by applying the “Inverse conversion” method with a feedback path and for calibration inside the ADC. The finally presented “Algorithmic Tracking ADC” with “Inverse conversion” is significantly superior to the standard Tracking ADC, and even compared to SAR ADCs implemented in a similar technology. The measurement done for the second implemented ASIC yields an ENOB of 7.64 bit, which is close to the theoretical limit of 8 bit, but offers with a conversion rate of 1.39 MS/s and 277.26 Mbit/s and a bandwidth of 3.8 MHz already very attractive results. Applying the method of “Tracking and correction” for compensation of nonlinearities, the SINAD could be measured to 36.72 dB, which corresponds to an effective resolution of 5.81 bit. With the superior compensation method “inverse conversion”, the SINAD improves to 42.01 dB corresponding to 6.68 bit resolution. The power consumption of the ASIC-2 with “inverse conversion” in a 65nm technology could be measured to 4.08 mW (resp. 211.2 fJ/c.s.) and is slightly higher compared to the “tracking and correction” method with 3.56mW (129.2 fJ/c.s.). With the extension of the methods and linearization algorithms towards a 28nm technology and also 12 bit we wanted to confirm the applicability of the approach and the validity of the results towards more demanding specifications. This third ASIC has been manufactured, but due to the manufacturing error could not been fully verified, so we can only refer to postsilicon simulations. However, even the post-silicon simulations show with a step-generation frequency of 4 GHz an average conversion rate of 723 MS/s (comparing to 308 mS/s for 65nm) and an average effective resolution of 10.14 bit (SINAD: 62.80 dB), which again shows the superiority of the “inverse conversion” method. Overall, the energy efficiency of this ASIC-3 is with 9,8 FJ/c.-s. 13x improved compared to ASIC-2, which shows that the advantages of this mostly digital ADC are even more dominant for modern technologies. Even with the comparison to a Pipeline SAR ADC with 12.1 fJ/c.-s. and an information density of 276.3 G Info/s the advantages of the algorithmic ADC are imminent, which delivers here 815.8 G Info/s. Finally it can be concluded that the advantage with recent semiconductor technologies, which are most built for digital architectures towards extreme transistor density and low power, yield opportunities for niche architectures, such as the one of the tracking ADC, which is typically used for e.g. controlling a slow changing voltage. The high algorithmic, but digital effort, is become increasingly less problematic and the overall architecture becomes more and more attractive (from layout area and power consumption point of view, but also due to the semicustom design methodology). The comparator remains the only central analog component, but it has been shown that its nonlinearities and nonidealities can be compensated with the method of “inverse conversion”. The required algorithmic effort is mostly digital in nature and is therefore not a blocking issue. Therefore, the “algorithmic tracking ADC” in the focus of this project has been shown to be an attractive alternative to SAR-ADCs, and shows a significant improvement compared to a standard tracking ADC.
Publications
- A Reconfigurable Arithmetic ADC for FPGA Implementations. In: ITG-Fachbericht, 293. In: Analog 2020; 17th ITG/GMM-Symposium, S. 11-15, VDE, Online, ISBN 978-3-8007-5335-2 28.-30. September 2020
Oliver Bachmann, Klaus Hofmann
- Oversampled Self-Adaptive Tracking (OSAT) Analog to Digital Converter. patent DE 102019115612A1. Dec. 2020
Oliver Bachmann and Klaus Hofmann
- “A novel Approach for Extending the Bandwidth Limitation of Tracking-ADCs”. In: 9th International Conference on Modern Circuits and Systems Technologies (MOCAST). 2020
Oliver Bachmann and Klaus Hofmann
(See online at https://doi.org/10.1109/MOCAST49295.2020.9200297) - Dissertation Algorithmic Tracking Scheme Analog-to-Digital Converter (Verlagsversion) Darmstadt, Technische Universität
Oliver Bachmann
(See online at https://doi.org/10.26083/tuprints-00018553) - Self-Adaptive-Correction-Unit (SACU) for timecontinuous Analog to Digital Converter. patent: DE 102020102931. Aug. 2021
Oliver Bachmann and Klaus Hofmann
