Suspension-Aware Designs and Analyses for Real-Time Embedded Systems

• Applicant: Professor Dr. Jian-Jia Chen
• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: from 2018 to 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 398602212

In computing systems, a job may suspend itself, due to the interactions with external I/O devices or accelerators, multicore systems with shared resources, suspension-aware multiprocessor synchronization protocols, etc. For real-time embedded systems, self-suspension behavior negatively impact the schedulability of real-time tasks and typically cause substantial performance/schedulability degradation. Even though some seemingly positive results have been reported for tackling self-suspending task systems in the past, a recent investigation led by the proposal applicant, Prof. Dr. Jian-Jia Chen, indicates that a significant portion of the literature (and also the majority of these results) before 2013 has been seriously flawed. Since most results before 2013 were in fact flawed (or with incomplete proofs), the investigation of self-suspending task models in real-time embedded systems has been restarted since 2015. This project intends to investigate robust and solid fundamental algorithms and analyses to carefully mitigate (via safe and sound execution/suspension enforcements) and analyze (via tight schedulability tests) the impact of self-suspending behavior in modern real-time embedded systems. The targeting systems are safety-critical systems with real-time requirements. Since the self-suspending behavior can introduce a high degree of complexity, new scheduling strategies or revisions of existing scheduling strategies are required. Our project intends to provide fundamental breakthrough in the scheduling theory and the corresponding schedulability analysis to flexibly accomodate the self-suspension behavior without introducing much pessimism when considering the worst-case timing behavior. With the scheduling strategies and schedulability tests provided in this project, we aim to offer tools for real-time system designers so that further optimizations by considering the perspectives of controllers, communications, and computation are possible.

• DFG Programme: Research Grants