Highly-scalable (hybrid-) beam-forming RF-receiver architecture

• Applicant: Professor Dr.-Ing. Friedel Gerfers
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2018 to 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 397976366

• Final Report Year: 2022

Final Report Abstract

In this project we investigated the architectural advance of sample based beam-forming receivers required for future energy-efficient large-scale beam-forming RF transceivers. A mathematically and architecturally study was performed to extract imperfections caused by finite phase-resolution and parasitic effects. Therefore, a simplified system model of a 12 GS/s 2x1 sub-sampling beamforming track-and-hold (SSBS-TH) was evaluated. The system-model where brought to transistorlevel (simulations) in a 22nm FDSOI CMOS technology and the outcome was shared with the research community. A summing gain of 4.4dB where achieved with an SFDR greater than 57 dBc and an SNR above 53 dB. Furthermore, the performance of a single sampler without beamforming capability was evaluated on chip level. The fabricated 6 GS/s sampler (2x timeinterleaved) has been successfully used active body biasing for the first time to improve the bandwidth, settling performance and leakage. Time-interleaving errors where investigated and calibrated off-chip using MATLAB. An SFDR beyond 64 dBc up to 2.8 GHz and an SFDR >60 dBc for a 3 GHz input where achieved and is above state-of-the-art. The SNR remains above 55 dBFS, while an overall bandwidth of 4.5 GHz is measured enabling wide-band sampling. The total power consumption of the chip is only 178 mW from a triple 2 V/0.9 V/-0.8 V supply. A second chip was designed and fabricated to increase the sampling speed to 12 GS/s and to reduce the jitter by using a different sampling architecture and thus a less complex clock generation. An SFDR > 58 dBc till 6 GHz is achieved and the SNR remains above 55.5 dB where the measured jitter amounts only 26.3 fs. The power dissipation is only 143 mW from a triple 2 V/0.9 V/-0.8 V supply. Further investigations would be necessary to implement the sampler in the SSBS-TH including the ADC to build a power-efficient beam-forming receiver.

Publications

• “Body Biasing Techniques in CMOS FD-SOI for Mixed-Signal and RF Designs, “, in IEEE ICECS, Italy, 2019
  F. Gerfers and N. Lotfi and E. Wittenhagen and H. Ghafarian and Y. Tian and M. Runge
  
• “A Beam-Forming Track and Hold Amplifier, “ in Analog 2020 – 17. ITG/GMM-Fachtagung
  E. Wittenhagen and M. Runge and F.Gerfers
  
• “A Sub-Sampling Beam-Forming Summation Track and Hold for Software Defined Radio, “ in IEEE ISCAS 2020, Sevilla
  E. Wittenhagen and M. Runge and W. Keusgen and F.Gerfers
  
• “Mixed-Signal Beamforming and Down-Conversion Receiver”, TUB / Frauenhofer Institute, HHI, May 2020
  F. Gerfers, W. Keusgen
  
• "A 3 GS/s >55 dBFS SNDR Time-Interleaved RF Track and Hold Amplifier with >67 dBc SFDR up to 3 GHz in 22FDX," in IEEE RFIC, USA, 2021
  E. Wittenhagen, P. Artz, P. Scholz and F. Gerfers
  
• “Advanced Mixed Signal Concepts Exploiting the Strong Body-Bias Effect in CMOS 22FDX®“, TCAS-I, 2021
  E. Wittenhagen and M. Runge and N. Lotfi and H. Ghafarian and Y. Tian and F. Gerfers