MRAM Based Design, Test and Reliability for ultra Low Power SoC
Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
Final Report Abstract
In any computing system, data storage and data movement are crucial steps. While technology scaling has provided benefits in terms of area reduction and performance improvements, both of dominant SRAM and DRAM memory technologies are facing various challenges, making them very hard to scale any further. Additionally, these memories are volatile, meaning that they lose their contents when they are powered off. While the amount of static (aka leakage) energy is increasing for these technologies, power gating strategies are not very straightforward for such memories as they lose their content and the valid data in such memories need to be saved somewhere else before they can be powered off. Due to these challenges, non-volatile memory technologies are very desirable for the replacement of on-chip SRAM and DRAM memories, particularly for normally-off and instanton computing to save leakage energy. Among several emerging non-volatile technologies, sprintronic memories, such as spin transfer torque (STT), have gain lots of interest in both industry and research communities due to several attractive features such as non-volatility, high density, high retention, high endurance and CMOS compatibility. However, there are several reliability and testing issue of this emerging technology which should be resolved, before widespread deployment. While the switching behavior of spintronic memories is inherently stochastic, the variability in the read and write operations of these memories should be modeled and accounted for at the design level. Additionally, the source of yield detractions in this technology should be understood and proper yield improvement techniques should be devised. At the same time the manifestation of manufacturing defects in this technology is very different than conventional CMOS-based memories, due to additional magnetic layers. Therefore, proper fault modeling for spintronic memories should be performed and accordingly, specific memory test patterns need to be developed for MRAM memories. The objective of this research project was to investigate, analyze, design, and optimize the use of non-volatility offered by STT-MRAM in a hybrid CMOS/MRAM normally-off computing architectures, and more especially in the context of ultra-low-power devices. The goal was to evaluate the full potential of this technology combined with an advanced CMOS technology by covering various aspects of cell, array, memory hierarchy, and architecture design as well as fault modeling, design for test, reliability, and robustness. We also developed a MRAM-based holistic design methodology, from cell to architecture-level, by designing a set of modeling, design, and simulation tools from circuit to system levels to design and evaluate hybrid memory hierarchy and processor architecture. We particularly explored reliability and test challenges in spintronic memories and provide proper models and techniques to analyze the variation effects in this technology, perform yield modeling and design for yield explorations, and finally perform reliability evaluation, design for reliability as well as defect characterization, fault modeling and test pattern generation for STT-MRAM memories.
Publications
- Fault tolerant non-volatile spintronic flip-flop. In 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) 2016 Mar 14 (pp. 261-264). IEEE
Bishnoi R, Oboril F, Tahoori MB
- "VAET-STT: A Variation Aware STT-MRAM Analysis and Design Space Exploration Tool", in IEEE Transcactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2017
S. Mohanachandran Nair, R. Bishnoi, M. S. Golanbari, F. Oboril, F. Hameed, and M. B. Tahoori
(See online at https://doi.org/10.1109/TCAD.2017.2760861) - “Efficient Testing of a Magnetic Memory Circuit”, 2017, (EU Patent No: 17001784.2-1203)
R. Bishnoi, F. Oboril, and M.B. Tahoori
- “Magnetic Probe Based Test Methodology for Spintronic Technologies”, 2017, (EU Patent No: 17401042.1-1568)
R. Bishnoi, F. Oboril, and M.B. Tahoori
- "Defect Injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM", In Proceedings of International Test Conference (ITC), 2018, USA
S. Mohanachandran Nair, R. Bishnoi, M.B. Tahoori, G. Tshagharyan, H. Grigoryan, and G. Harutyunyan
(See online at https://doi.org/10.1109/TEST.2018.8624725) - "Parametric Failure Modeling and Yield Analysis for STT-MRAM", in proceedings of Design, Automation & Test in Europe (DATE), 2018, Germany
S. Mohanachandran Nair, R. Bishnoi, and M. B. Tahoori
(See online at https://doi.org/10.23919/DATE.2018.8342016) - “Multi-Bit Non-Volatile Flip-Flop”, 2018, (EU Patent No: 18000262.8)
R. Bishnoi, C. Münch, M.B. Tahoori
- "A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2019
S. Mohanachandran Nair, R. Bishnoi, M. B. Tahoori
(See online at https://doi.org/10.1109/TVLSI.2019.2904197) - "Fast and Reliable STT-MRAM Using Non-uniform and Adaptive Error Detecting and Correcting Scheme", in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), 2019
N. Sayed, R. Bishnoi, and M.B. Tahoori
(See online at https://doi.org/10.1109/TVLSI.2019.2903592) - "Mitigating Read Failures in STT- MRAM", in proceedings of VLSI Test Symposium (VTS), 2020, USA
S. Mohanachandran Nair, R. Bishnoi, and M.B. Tahoori
(See online at https://doi.org/10.1109/VTS48691.2020.9107605)
