1-D Multi-Gate FETs: Tailoring the Potential Landscape on the Nanoscale

• Applicant: Professor Dr. Joachim Knoch
• Subject Area: Electronic Semiconductors, Components and Circuits, Integrated Systems, Sensor Technology, Theoretical Electrical Engineering
• Term: from 2015 to 2017
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 266030637

One-dimensional (1-D) materials such as nanowires and nanotubes have attracted a great deal of attention recently as buildings blocks of future nanoelectronics systems. This interest is in part due to the small geometry that allows realizing optimum scalability of the devices due to the strong electrostatic gate control in e.g. wrap-gate device structures. In addition, nanowires/tubes enable one-dimensional electronic transport that has a number of benefits such as a rather long mean free path for scattering or the highly linear transfer characteristics. Furthermore, the combination of 1-D transport and excellent gate control enables a tight control over the potential distribution within the device. While it is common practice to use gates in order to manipulate the potential profile of transistor device based on novel materials so far only a small number of gates has been used and these gates exhibit a length on the order of several tens to hundreds of nanometers and/or are placed far apart from each other prohibiting a manipulation of the potential profile on the nanoscale. The aim of the present proposal is to realize a 1-D multi-gate device architecture where a large number of gates (on the order of 10 and more) with lengths in the few nanometer range will be placed next to each other with a few nanometers inter-gate distances. This device layout allows tailoring the conduction/valence band profile along the device on the nanoscale due to the excellent gate control in 1-D nanostructures; hence this band tailoring allows studying the full potential of 1-D structures for nanoelectronics. Two different demonstrations will be pursued within the project: First, a gate-induced superlattice structure will be realized in e.g. carbon nanotubes and/or InAs nanowires. With appropriate dimensions this superlattice will serve as an energy filter enabling a so-called steep slope transistor that operates at very low supply voltages and hence facilitates ultra-low power nanoelectronics systems. Second, we will adjust the band profile along the channel in order to maximize the linearity of the transfer characteristics of the 1-D device.

• DFG Programme: Research Grants