Invasive NoCs & Memory Hierarchies for Run-time Adaptive MPSoCs (B05)

• Subject Area: Security and Dependability, Operating-, Communication- and Distributed Systems
• Term: from 2010 to 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 146371743

The investigations will tackle the scalability of the invasive manycore architecture to overcome potential limitations and bottlenecks regarding the on-chip communication and memory hierarchy. The invasive Networks-on-Chip will be extended towards a flexible, multi-layered and hierarchical architecture. Furthermore, improvements of the memory architecture such as near-memory acceleration and data migration within distributed-shared-memory hierarchies will be explored. A major goal for all these extensions is to provision guarantees for non-functional properties to hold under runtime changes.

• DFG Programme: CRC/Transregios
• Subproject of: TRR 89: Invasive Computing
• Applicant Institution: Friedrich-Alexander-Universität Erlangen-Nürnberg
• Project Heads: Professor Dr.-Ing. Jürgen Becker; Professor Dr. Andreas Herkersdorf; Professor Dr.-Ing. Jürgen Teich, until 6/2018