Adaptive Application-Specific Invasive Micro-Architectures (B01)

• Subject Area: Computer Architecture, Embedded and Massively Parallel Systems
• Term: from 2010 to 2022
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 146371743

The i-Core is a processor with a run-time adaptive micro architecture (uArch, e.g. dynamic L1 cache configuration) and a run-time reconfigurable fabric for appl.-specific Special Instr. (SIs). In the first two phases, we investigated invading its reconfigurable fabric and uArch, generating SIs automatically on-the-fly, extending it to a reconfigurable multi-core processor, reallocating the intra-tile cache dynamically, and developing a WCET analysis. The Phase III focus is on run-time requirement enforcement (enforcing WCETs and security requirements), and optimisations (e.g. by using approximated accelerators and control flow within SIs).

• DFG Programme: CRC/Transregios
• Subproject of: TRR 89: Invasive Computing
• Applicant Institution: Friedrich-Alexander-Universität Erlangen-Nürnberg
• Project Heads: Dr.-Ing. Lars Bauer; Professor Dr.-Ing. Jürgen Becker; Professor Dr.-Ing. Jörg Henkel; Professor Dr.-Ing. Michael Hübner, until 4/2012