SFB 912:  HAEC - Highly Adaptive Energy-Efficient Computing

• Subject Area: Computer Science, Systems and Electrical Engineering
• Term: from 2011 to 2020
• Project identifier: Deutsche Forschungsgemeinschaft (DFG) - Project number 164481002

The energy consumption and the resulting ecological impact of main Internet components as data centers and the communications infrastructure are reaching alarming levels. In 2012, information and communication technology accounts for 4.6% of the worldwide electricity consumption with annual growth rates of 7% corresponding to a doubling per decade. Communication networks, computers, and data centers are equally responsible for the aforementioned energy consumption. The visionary goal of the Collaborative Research Center (CRC) HAEC (Highly Adaptive Energy-Efficient Computing) is to research technologies to enable computing systems with high energy-efficiency without compromising on high performance.Certainly, a straightforward way for improving energy efficiency is to reduce the energy consumption of every individual hardware component involved. However, it is equally important to understand how the software system can be adapted to the hardware and vice versa. Today, software is written without being energy-aware and is mapped agnostically onto generic hardware configurations of parallel machines. As the computational problems require a certain amount of problem-specific processing and intercommunication, a highly adaptive hardware system, which can optimize its configuration according to the needs of the software system, could generate a much higher level of efficiency. For this, system states of the application and hardware system need to be monitored and taken into account during run-time as well. In this regard, HAEC will concentrate on researching larger server systems, by innovating from applications to hardware.To achieve an integrated approach of highly adaptive energy-efficient computing (HAEC), the problem is approached at all levels of technology involved, the hardware, the computer architecture and operating system, the software modeling as well as the application modeling and runtime control levels. A novel concept is explored, the HAEC Box, involving optical and wireless chip-to-chip communication. This allows for a new level of run-time adaptivity, creating a platform for flexibly adapting the hardware configuration to the needs of the computing problem. To exploit this capability at the software level, a hierarchical energy-control loop infrastructure is researched, which is responsible for the control of the energy trade-off based on the current hardware state as well as the context-aware application requirements. Hence, the HAEC CRC is a first attempt to achieve high adaptivity and energy efficiency with an integrated approach going through all levels, from hardware components all the way to the application software.In Phase I, we broke the ground for the HAEC vision by coming up with significant progress in novel technologies as well as generating ideas for the realization of this vision. In Phase II we have picked up these ideas to show revolutionary approaches that drastically reduce the HAEC communications power consumpti

• DFG Programme: Collaborative Research Centres

Completed projects

• A01 - Millimeter-Wave Integrated Circuits for Ultra High-Speed Wireless Board-to-Board Computer Communication (Project Head Ellinger, Frank )
• A02 - Ultra High-Speed Wireless Board-to-Board Computer Communication (Project Heads Dörpinghaus, Meik ;  Fettweis, Gerhard P. ;  Fischer, Andreas )
• A03 - Efficient Cooperative Communications in Multi-hop Networks (Project Head Jorswieck, Eduard Axel )
• A04 - Modeling Performance and Power Consumption of Energy-Aware Software on a Highly Adaptive Computing System (Project Head Nagel, Wolfgang E. )
• A05 - Antennas and Characterization for Adaptive Wireless Backplane Communication (Project Head Plettemeier, Dirk )
• A06 - Compact Modelling and Experimental Power Amplifier Design and Characterization for 180 GHz Transmission (Project Head Schröter, Michael )
• A07 - Design of Broadband Integrated Circuits for Energy-Adaptive Optical Onboard Links for Inter-Chip Communication (Project Head Ellinger, Frank )
• A08 - Distributed Cross-Layer Security for Dynamic Networks (Project Heads Franz, Elke ;  Jorswieck, Eduard Axel ;  Strufe, Thorsten )
• A10 - System integration for optical and wireless Pbit/s communication in high performance computing (Project Head Bock, Karlheinz )
• A11 - Monolithic Photonic Transceiver for On-board Optical Communication (Project Head Jamshidi, Ph.D., Kambiz )
• A12 - Energy-efficient Routing Mechanisms for Board-to-Board Communication on the HAEC Box (Project Head Strufe, Thorsten )
• A13 - Distributed Coded Computing for the HAEC Box (Project Head Fitzek, Frank Hanns Paul )
• B01 - Energy-Aware Software Architectures (Project Head Aßmann, Uwe )
• B02 - Semantic Technology for Context Awareness (Project Heads Baader, Franz ;  Turhan, Anni-Yasmin )
• B03 - Formal Methods for Quantitative Analysis and Optimization of Energy Models (Project Head Baier, Christel )
• B04 - Energy-Aware Resource Management (Project Head Härtig, Hermann )
• B05 - Highly Adaptive Energy-Aware Data Processing Platform for In-Memory Applications (Project Head Lehner, Wolfgang )
• B06 - Energy-Aware Service Execution (Project Heads Dargie, Ph.D., Waltenegus ;  Schill, Alexander )
• B07 - Languages and Compilers for Energy-Efficient Programming (Project Head Castrillon-Mazo, Jeronimo )
• B08 - High-Capacity Knowledge Processing Pipeline (Project Head Krötzsch, Markus )
• Z01 - Central Tasks (Project Head Fettweis, Gerhard P. )

• Applicant Institution: Technische Universität Dresden
• Spokesperson: Professor Dr.-Ing. Gerhard P. Fettweis