We have successfully shown the benefits of a system concept based on tightly integrated multi-grained reconfigurable tiles that is able to satisfy and improve execution performance compared to state-of-the-art approaches. This has been achieved by novel contributions in each of the three research areas that are closely related to each other. On the hardware side, a novel reconfigurable architecture on tile granularity has been realized. Different to state-of-the-art, the advantages of this architecture are the ease of high-level programmability as well as the possibility to realize highly optimized accelerators based on a common hardware substrate. The architecture is therefore composed out of tightly interconnected reconfigurable tiles. The microarchitecuture of these tiles has specifically been designed to meet different requirements: low hardware complexity, scalability to flexibly combine tiles to heterogeneous processor instances, efficient high-level programming support, high performance for both general purpose processors as well as accelerators, and small reconfiguration costs. Compliance with these objectives has been obtained by a careful analysis of general purpose processor as well as accelerator requirements for the definition of a common hardware substrate that both modes can share and a well defined co-design of complex tasks between hardware and compile time. As a result, our developed tile-based reconfigurable architecture supports resource-aware adaptation to diverse applications, support for different models of parallel programming, reduces programming complexity through support for smooth application improvement, reduces diversity of core architecture variants thus simplifying the hardware design process. For supporting the flexibility introduced by reconfiguration of the hardware architecture, a novel flexible Software Framework was necessary. The problem here is that dependent on the hardware configuration also the interface to the software, the Instruction Set Architecture (ISA), changes. Thus, a software framework that supports parallel code generation for multiple ISAs is required. The software framework consists of three components: A mixed-ISA compiler, mixed-ISA binary utilities, and a mixed-ISA simulator. All components are kept user-retargetable by a novel Architecture Description Language (ADL) including all supported ISAs as well as to enable design-space exploration and support for custom instructions. The developed KAHRISMA compiler features mixed-ISA software development by generating several ISA alternative of one function in one compilation run as well as supporting mixed-ISA application development that change their ISA/configuration at run time. The binary utilites support the mixed-ISA code generation on the assembler and linker level. The overall framework is evaluated by the mixed-ISA simulator that also supports the reconfiguration on instruction-level for the simulation. Our run-time system enables efficient simultaneous multi-tasking in reconfigurable processors with functional block level allocation of the multi-grained reconfigurable fabric while maintaining the application’s QoS requirement under run-time varying scenarios. Additionally, it provides a dynamic trade-off between performance and available area of multi-grained fabrics by selecting multi-grained instructions. Our Constraints-based Resource-Distributor adaptively allocates the fabric to different tasks considering their refined performance constraints and criticalities such that the number for deadline misses are reduced. The On-Demand Resource-Lender enables the situation dependent optimization by further utilizing the available configured EDPEs, which are temporarily not in use of the owner tasks. Compared to state-of-the-art, our scheme reduces the deadline misses by (on average) 3×, while improving the overall performance by 1.3×. Furthermore, our novel run-time system fully exploits the adaptivity provided by multi-grained ISEs by using intermediate ISEs and mono-CG extensions. We showed the applicability of our proposed run-time system on state-of-the-art processors like Morpheus, 4S, and RISPP and we showed the benefits that the KAHRISMA architecture provides.