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Institution
Technische Universität München
Fakultät für Elektrotechnik und Informationstechnik
Lehrstuhl für Entwurfsautomatisierung
Address
Arcisstraße 21
80333 München
Deutschland
GERiT
This institution in GERiT
80333 München
Projects
Research Grants
Current projects
Bandwidth Maximization and Allocation for Wavelength-Routed Optical Networks-on-Chip (WRONoC)
(Applicant
Tseng, Tsun-Ming
)
Design and Integration of Test Module for Microfluidic Large-Scale Integration (mLSI)
(Applicant
Tseng, Tsun-Ming
)
Design Obfuscation with Sequential Timing to Counter Reverse Engineering
(Applicants
Li, Bing
;
Schlichtmann, Ulf
;
Sigl, Georg
)
Exploring Efficient and Robust Optical Accelerators for Neural Networks
(Applicant
Schlichtmann, Ulf
)
Learning-based Efficient and Accurate Timing Analysis of Integrated Circuits
(Applicant
Schlichtmann, Ulf
)
Physical Design for Microfluidic Large-Scale Integration with Partitioning and Floorplanning
(Applicant
Tseng, Tsun-Ming
)
Reliability and Robustness Enhancement of RRAM-based Neuromorphic Computing
(Applicants
Schlichtmann, Ulf
;
Zhang, Li
)
Completed projects
Analytische Plazierverfahren mit erweiterter Funktionalität
(Applicant
Antreich, Kurt J.
)
Application of a Generative Grammar for the Automated Architectural Exploration of Digital System-on-Chip (SoC) Platforms
(Applicant
Schlichtmann, Ulf
)
Combining Topology Synthesis and Physical Design for Wavelength-Routed Optical Networks-on-Chip (WRONoC) — Design Automation Using Physical Layout Templates
(Applicant
Schlichtmann, Ulf
)
FPGA-Synthese für sequentielle Schaltungen mittels kombinatorischer und sequentieller Logiksyntheseverfahren
(Applicant
Antreich, Kurt J.
)
Methods for automatic optimization of analogue integrated circuits with regard to ageing
(Applicant
Gräb, Helmut
)
Verification and synthesis of structural features of analog/mixed-signal circuit using constraint programming exampled by ESD and level shifting
(Applicant
Gräb, Helmut
)
Priority Programmes
Completed projects
Lifting Device-Level Characteristics for Error Resilient System Level Design: A Crosslayer Approach
(Applicant
Schlichtmann, Ulf
)
Simulationsbasierter Testentwurf für gemischt analog-digitale Systeme
(Applicant
Antreich, Kurt J.
)
CRC/Transregios
Completed projects
Generation of Distributed Monitors and Run-time Verification of Invasive Applications
(Project Heads
Müller-Gritschneder, Daniel
;
Schlichtmann, Ulf
;
Schmitt-Landsiedel, Doris
)
Additional Information
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